The present disclosure relates to a memory control apparatus, memory control method, information processing apparatus and program. Especially, the present disclosure relates to a memory control apparatus, memory control method, information processing apparatus and program that can reduce the power consumption of a main storage apparatus.
There is suggested a technique of suppressing the power consumption of the whole system by an idle state such that a task is not assigned to a specific CPU core in a multi-core processor including a plurality of CPU cores (for example, see Japanese Patent Application Laid-Open No. 2011-70661).
Also, in a multi-core configuration system including a power-saving CPU core and a high-performance CPU core, there is an operation of switching between the power-saving CPU core and the high-performance CPU core according to the load condition of the system (for example, see ARM Holdings, Inc., homepage, [search on Apr. 2, 2012] Internet, <URL http://www.arm.com/ja/products/processors/technologies/bigLITTLEprocessing.php>).